![]() ![]() When the execution engine figures out the actual target doesn’t match the predicted one, it has to squash wrongly fetched instructions and wait for instructions to be delivered from the correct path. An incorrect guess means fetching down the wrong path, hurting performance. Branch Prediction: A Significant AMD Leadīranch predictors guess where to fetch instructions from without waiting for branch instructions to execute. Then, we can guess at how much a certain metric impacts performance. That lets us see if portions of CBR15 that have higher cache hitrates or lower mispredicts also have better IPC. Because we’re sampling performance counters at 1 second intervals, we can plot IPC versus various metrics. Over 40% of instructions access memory, with a roughly three times as many loads as stores.Įvery tile in CBR15 has different characteristics. Curiously, there are almost twice as many FP64 multiplies (6.51%) as FP64 adds (3.73%). Floating point calculations are dominated by FP64, with a bit of FP32 sprinkled in. Most executed SSE instructions are scalar, so the benchmark does not heavily stress the CPU’s vector units. Not all instruction categories are included here, and some categories overlap.ĬBR15 uses a lot of SSE instructions (41.7%), and doesn’t take advantage of AVX. Benchmark Overview Cinebench R15 instruction composition, collected using Intel’s Software Development Emulator (SDE). In short, Zen 2 pulls ahead thanks to its superior branch predictor, larger mid-level cache, and ability to track more pending floating point micro-ops in the backend. It can utilize all available CPU threads, but here we’ll be analyzing it in single thread mode. Cinebench R15 (CBR15) is a popular benchmark based on Cinema4D’s 3D rendering engine. ![]()
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